Perfоrm the fоllоwing if you hаve not аlreаdy done so: Show your workspace (desk top) and the front wall that you are facing. Hold up both sides of all your scratch paper on camera before you start. It's a required procedure to maintain academic integrity. A penalty may be applied if you fail to do so. Please complete this quiz on your own with no outside help. Do not use any unauthorized aids including lecture notes, formula sheet, calculators, dual devices, and other online resources. Do not work with other people. Do NOT disconnect webcam or Honorlock before you submit your work. Typing in your name in the box below signifies the following statement: On my honor, I have neither given nor received unauthorized aid doing this exam.
Prоblem 1) D register with reset аnd enаble with prоcedurаl cоde Write a D register module, with an asynchronous reset and a synchronous enable, parameterize inputs and output arrays with parameter Size with default 8. (hints: see the cheat sheet, enable enables the D register output Q to change based on input D) You will need inputs clk, reset, enable, and input D of width Size, and output Q of width Size (you don't need a Qnot). Remember this is a D register which is like Size flipflops in parallel. You will be using your D register in several problems in this test. Note: reset should reset the register whether it is enabled or not, that is the way asynchronous resets work. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype, use one more appropriate for System Verilog. Declare all variables (some declarations are in the module statement), avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don't use compiler directives or short cuts.