Mаke а cоunter mоdule thаt cоunts from 0 up to MaxVal and then once it gets to MaxVal stops counting. For this counter, after reaching MaxVal the count doesn't change on additional clock cycles. (if MaxVal is 5 it would count 0,1,2,3,4,5,5,5,5,5,5 ... of course you can't assume MaxVal is 5 this is just an example to make sure you understand the problem) Your counter will need clk, and reset inputs, and you need to output the current count, use an array named Count. Use parameter Size for the width of output Count, and input MaxVal. Use a default parameter Size of 3 bits. For full credit write the module instantiating the D register you designed above. By instantiating the D register module you should not need to have an always block in the counter module, and points may be deducted. If you duplicate the function of instances in procedural code, it will be counted incorrect. Your solution should be succinct and well organized. For full credit Indent all blocks for full credit. Your code should be efficient and succinct. For full credit you must productively use instances to make the counter count. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don't use compiler directives or short cuts.
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