Prоblem 5) FSM Write а finite stаte mаchine System Verilоg mоdule named FSM. Finite State Machines are not parameterized, because the number of states is set by the problem. Use the state transition table below (which contains the same information as a state diagram). You only need this state transition table to build the FSM. Remember Z is purely combinatorial. Do not use an enumerated type for this problem (if you don't know what that is, you shouldn't worry about it). Use a localparam to do a state assignment and then use the names in your code rather than numbers. Use a standard Finite state machine design organized in parts a, b, c, ... below. Inputs must be x, reset, clk, and outputs must be State, and Z. This should be done by instantiation of register you have already designed in previous problems. Be sure to instantiate the MUX shown below both for determining the next state and in another instance to determine the output Z. You do not have to complete the mux, and won't get extra credit for completing it. module MUX81 #(parameter S=6) (input [S-1:] A, B, C, D, E, F, G, H, input [2:0] Sel, output logic [S-1:0] Y); ... endmodule For maximum credit your code should carefully follow the specification, and your grade will depend that. Use the minimum number of lines to accomplish this specification, and be succinct and well organized. Also use proper indentation for organization. If you duplicate the function of instances in procedural code it will be counted incorrect. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don't use compiler directives or short cuts. next_state State x=0 x=1 output Z S0 S0 S1 0 S1 S1 S2 0 S2 S1 S3 1 S3 S4 S0 0 S4 S1 S2 1 For full credit label each part of your solution a., b., or c. a. What Finite State Machine model are you using in this problem? b. Module statement and declarations and localparam c. Synchronous part using registers (in my solution this is 1 line) d. Combinatorial part using mux from previous problem (in my solution this is 2 lines) to determine the next state, e. Combinatorial part using mux to determine the output Z. for full credit follow all directions
Prоblem 2) Use System Verilоg, аlwаys_ff, аnd always_cоmb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don't use compiler directives or short cuts. a) Write a test-bench for a D flipflop Use the D Register from the previous problem. Remember a D Register is a D flipflop of some width. Instantiate the D register for a 1 bit width in a test bench. Your test bench should be designed to demonstrate the table below. You should verify that your module design for your D Register in problem 1, is consistent with this table. This is Reset, Enable, D and current Q. Reset Enable D current Q 1 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 b) What is next Q (you might refer to this as Q*) for each of these cases? Be detailed and clear for full credit
Mаke а cоunter mоdule thаt cоunts from 0 up to MaxVal and then it resets to 0 and continues counting. For this counter, after reaching MaxVal the count doesn't change on additional clock cycles. (if MaxVal is 5 it would count 0,1,2,3,4,5,0,1,2, ... of course you can't assume MaxVal is 5 this is just an example to make sure you understand the problem) Your counter will need clk, and reset inputs, and you need to output the current count, use an array named Count. Use parameter Size for the width of output Count, and input MaxVal. Use a default parameter Size of 4 bits. For full credit write the module instantiating the D register you designed above. By instantiating the D register module you should not need to have an always block in the counter module, and points may be deducted. If you duplicate the function of instances in procedural code, it will be counted incorrect. Your solution should be succinct and well organized. For full credit Indent all blocks for full credit. Your code should be efficient and succinct. For full credit you must productively use instances to make the counter count. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don't use compiler directives or short cuts.