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In the Tomasulo algorithm, what do the dispatch and scheduling units do?

There are two database benchmark programs X and Y. Computer A can process 4 transactions per second of benchmark X and 4 transactions per second of benchmark Y. Computer B on the other hand can process 2 transactions per second of X and 7 transactions per second of Y. If we care equally about the performance of both benchmarks, which computer should we choose? Why? 

22. Which analyte from the choices below is a metabolite of methionine that is very labile and can indicate thrombosis risk when elevated?

What is the point of studying computer architecture?

Could you schedule the above code in 2 cycles if you had enough function units? Why or why not?

Assume that the above processor also experiences an average of .2 stall cycles per instruction due to data hazards. Accounting for both stalls due to control hazards and due to data hazards, what is the speedup of this processor over an un-pipelined processor?

What is one way to reduce the Miss Penalty of a cache?

A SIMD processor can run any parallel program written for a MIMD processor.

Create an instruction stream with the following dependency graph. Recall that a regular arrow indicates a true dependence, a circle indicates an output dependence, and a cross indicates an anti-dependence.      Use only ADD instructions, and use the following format (the ID is the letter use for each instruction in the above diagram): ID: ADD DEST SRC1 SRC2    

In your own words, what is cache coherency and why do we care about it? No need to give the full definition, just explain what it is, and why it is useful for a shared memory system to to implement it.