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Questions 8-12 Consider an address stream where LD = Load an…

Questions 8-12 Consider an address stream where LD = Load and ST = Store: A. LD 0x000AB. ST 0x001BC. ST 0x002CD. LD 0x003DE. LD 0x004EF. ST 0x005FG. LD 0x0031H. ST 0x0022 The above address stream is run for 10 iterations on a (C = 6, B = 4, S = 0) cache that uses a write-back, write-allocate policy for a total of 80 Accesses. Answer the below questions:

Questions 13-16 Now a 2 entry victim cache with FIFO replace…

Questions 13-16 Now a 2 entry victim cache with FIFO replacement is added to the cache system described for Questions 8-12. Answer all the below questions considering this optimization: Address stream repeated for convenience A. LD 0x000AB. ST 0x001BC. ST 0x002CD. LD 0x003DE. LD 0x004EF. ST 0x005FG. LD 0x0031H. ST 0x0022

There are two database benchmark programs X and Y. Computer…

There are two database benchmark programs X and Y. Computer A can process 3 transactions per second of benchmark X and 5 transactions per second of benchmark Y. Computer B on the other hand can process 2 transactions per second of X and 7 transactions per second of Y. If we care equally about the performance of both benchmarks, which computer should we choose? Why?

Are there any compulsory misses when considering all iterati…

Are there any compulsory misses when considering all iterations of this address stream? If so, list the addresses (A-H) and the iteration (1-10) in which the address incurs a compulsory miss below. For example, if address X incurs a compulsory miss in iteration n, then answer {X : n}.

At ACME computing, a computer architect comes up with a nift…

At ACME computing, a computer architect comes up with a nifty device which when added to their premier CPU speeds up division instructions by 55 percent. How much faster will a program where 25 percent of instructions are division instructions will run with this modification (as compared to the unmodified CPU)?