OS_Structure_4c Microkernel The context for this question is…

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OS_Structure_4c Micrоkernel The cоntext fоr this question is sаme аs the previous question. 4. You аre building an OS using a microkernel-based approach following the principles of the L3 microkernel. The processor architecture you are building this OS for has the following features:      • A 32-bit hardware address space.    • Paged virtual memory system (8KB pages) with a processor register called PTBR that points to the page table in memory to enable hardware address translation.     • A TLB with Address space IDs associated with each TLB entry.     • A pair of hardware-enforced segment registers (lower and upper bound of virtual addresses) which limit the virtual address space that can be accessed by a process running on the processor.     • A virtually-indexed physically tagged processor cache. You end up with 2 big subsystems (A and B) that each require 230 bytes of virtual memory space. You also end up with 4 subsystems (C,D,E,F) that require 100x220 , 500x220 , 1000x220 , and 2000x220 bytes of virtual memory, respectively. You want to put each of these subsystems in their own protection domains.  c. [2 points] (Answer this question based on your grouping of the protection domains) There is a context switch from A to B. What does your OS do to facilitate this context switch? 

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